In a constant on time (COT) or hysteretic mode self-clocking DC-to-DC power converter system, generation of the pulse width modulation (PWM) signal relies on ripples of the output voltage to carry out triggering control. Large ripples are beneficial to loop stability; however, they may result in over specification conditions. On the contrary, small ripples could remain the system under specifications, while they are adverse to loop stability. Thus, it is a challenge to maintain loop stability with small output voltage ripples for design of the power converter system.
As shown in FIG. 1, a traditional COT ripple regulator system includes a high-side device Q1 and a low-side device Q2 connected to each other by a phase node Phs in series between a voltage input terminal Vin and a ground GND, a control circuit 10 to provide PWM signals UG and LG for controlling the high-side device Q1 and the low-side device Q2, respectively, to regulate an inductor current IL to charge an output capacitor Co to generate an output voltage Vout, and voltage divider resistors R1 and R2 divide the output voltage Vout to generate a feedback voltage Vfb1 for the control circuit 10. In FIG. 1, the resistor R3 represents the effective series resistance (ESR) of the output capacitor Co. In the control circuit 10, an error comparator 14 compares the feedback voltage Vfb1 with a reference voltage Vref to generate a comparison signal Sc, a PWM controller 12 triggers the PWM signal UG responsive to the comparison signal Sc, to control the high-side device Q1, and an inverter 16 inverts the PWM signal UG to generate the PWM signal LG for controlling the low-side device Q2. In the PWM controller 12, a constant time generator 18 determines the constant time Ton of the PWM signal UG, and a logic controller 22 generates a triggering signal St responsive to the comparison signal Sc for a one shot circuit 20 to trigger the PWM signal UG.
FIG. 2 is a waveform diagram of the circuit shown in FIG. 1 to illustrate operation of the COT ripple regulator system. Referring to FIGS. 1 and 2, at time t1, the feedback voltage Vfb1 becomes lower than the reference voltage Vref, so the comparison signal Sc turns to low from high and as a result, the logic controller 22 asserts the triggering signal St to trigger the PWM signal UG, to turn on the high-side device Q1 for a time period, i.e. the constant time Ton. During the high-side device Q1 is on, the feedback voltage Vfb1 increases, and then upon expiration of the constant time Ton, the high-side device Q1 is turned off and the low-side device Q2 is turned on, by which the feedback voltage Vfb1 decreases. When the feedback voltage Vfb1 again becomes lower than the reference voltage Vref, the high-side device Q1 is turned on again for the constant time Ton. By working with such a cycle, the COT ripple regulator system regulates the output voltage Vout at a default value.
However, in the case that a ceramic capacitor is used as the output capacitor Co, due to the very small effective series resistance R3 of the ceramic capacitor, the output voltage Vout and thereby the feedback voltage Vfb1 will have very small ripples, even could be regarded as DC signals, causing the COT ripple regulator system almost impossible to operate stably.